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Simply RISC S1 Core

Written by Administrator   
Monday 5 October 2009
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Simply RISC S1 Core is a cutdown version of the OpenSPARC processor released as open-source by Sun Microsystems. The current version is based on the latest OpenSPARC T1 v1.6.

While OpenSPARC T1 (codename Niagara) features 8 SPARC CPU Cores and several peripherals, Simply RISC S1 Core (codename Sirocco) takes only one 64-bit SPARC Core from that design and adds a Wishbone/AMBA bridge and a simple reset controller:

The whole process of designing a Wishbone bridge for the SPARC Core has been detailed in Chapter 11 of the book OpenSPARC Internals; the design now also supports an AMBA bridge as explained on the OpenSPARC project page at the University of Catania.

The enviroment contains scripts that support the use of three different "flavors" of the S1 Core; the following table summarizes the synthesis results obtained with Xilinx tools:

S1 Core versionDescriptionVirtex-5 Area (*)
S1 Core EEFour threads, usual 16K+8K L1 caches60K LUTs
S1 Core SEOne thread, usual 16K+8K L1 caches40K LUTs
S1 Core MEOne thread, no L1 caches37K LUTs

(*) Number of Slice LUTs on Virtex-5 devices, pre-Place-and-Route, obtained with provided push-button script

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Last Updated Monday 5 October 2009

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