Sunday 18 February 2018
Simply RISC

Main Menu
S1 Core

Simply RISC Board
Experimenting with the S1 Core on FPGA

Written by Administrator   
Friday 12 March 2010

by Dmitry Rozhdestvenskiy

The FPGA board "Xilinx ML507" on my desk inspired me to try to connect the S1 Core to the Xilinx DDR2 controller using the standard Wishbone bus.

So I did it. The first system I designed was like this:

Basically I had to write a parallel Flash reader and some glue-logic with a FIFO to connect the Xilinx DDR2 controller to the Wishbone bus. Then I had to insert a FIFO in the PCX channel to avoid the need to handle the original stall/resume mechanism.

I also binary-patched the single-thread OpenBoot PROM code (in file 1c1t_obp_prom.bin) to switch caches off, as the original Wishbone bridge did not contain the directories necessary for the correct L1-cache operation.

Finally I patched the UART speed, because the OpenCores UART has no separate clock-input and just divides the system frequency.

At this point the processor started fetching instructions from the Flash; but very soon I realized that some simplifications in the original bridge would not allow it to boot successfully.

In fact, there was no support for atomic instructions (CAS) at all. Adding such a support would make the state machine more complex, so I decided to rewrite the bridge.

I reused Fabrizio's concepts implemented in the original S1 Core bridge and the reference Microblaze code from the official OpenSPARC T1 release 1.7 (that code is guaranteed to be bug-free, since it can run even in a dual-core configuration).

When completed, the only patch needed is (again) the one for the UART speed. Now the bridge was able to boot the OpenBoot PROM completely!

But when we started to boot the Linux kernel we found out that it used floating-point operations. So I designed a new system for our new Stratix-IV development kit with a large FPGA, able to fit the whole core, including the FPU:

With this new system, now Linux boots correctly as single-thread! And even using PROM file 1c4t_obp_prom.bin, i.e. the four-threads version of the OpenBoot code, Linux starts booting.

So, what's left? First of all some debugging of the multi-threading, to understand why the four-threads version of Linux hangs after a while; and also try to make the Ethernet work. In fact, the OpenCores Ethernet controller has a software support starting from Linux kernel 2.6.30, so we will have to compile this new kernel for a SPARC target.

Another lack of this design is that, despite the fact that the new bridge implements nearly all PCX functionality, it will still not allow to build an SMP multiprocessor system because in such these machines the directory of the L1-cache should be able to send messages to other cores, and not only to the issuing one. But it seems an excellent base to build an L2-cache for a multi-core OpenSPARC system for FPGA, because it seems to be the much easier than adopting the original OpenSPARC code for the L2.

Learn more...



Last Updated Friday 12 March 2010

Top of the page